The size of semiconductor wafers (hereinafter also referred to as silicon wafers) used in semiconductor manufacturing is increasing in order to fabricate more chips per wafer and reduce the cost per chip. For instance, most state-of-the art manufacturing lines use 200 mm wafers, instead of the 125 to 150 mm wafers common only a few years ago. There are plans underway to convert to 300 mm wafers. Correspondingly, the raw wafer cost has become significant.
There is a shortage in the silicon wafer supply and new fabrication lines are being set up to meet the demand. The silicon wafers desirably meet certain specifications, such as thickness, uniformity, electrical resistivity, oxygen concentration, and surface smoothness (at least on one side). During wafer processing, wafers are rejected when devices are out of specification or when there is a quality problem. A typical yield loss in which a full wafer is rejected for being out of specification is typically about 5 to 10%, whereas the loss on an individual chip basis is typically about 20% or higher. Such yield losses increase the cost of silicon wafers.
In device manufacturing, different doped layers and regions are formed by epitaxial deposition, implantation, diffusion, and annealing. Selected regions of oxides and layers of oxide are formed by thermal oxidation of silicon or by chemical vapor deposition. These process steps typically alter the top 1 to 2 .mu.m of the silicon wafer. For wafers used in forming trench capacitors, narrow oxide-filled trenches often extend about 4 to 6 .mu.m into the silicon. Patterned layers of conductors (metal, silicides, or polysilicon--hereafter collectively referred to as metal) and insulators are formed over the devices in order to complete the wiring.
A typical wafer used in semiconductor manufacturing has the following specifications: thickness is 725.+-.20 .mu.m; substrate resistance is between 5 and 10 mohms-cm; warp (unchucked) is less than 65 .mu.m; global flatness is less than 5 .mu.m; oxygen concentration is between 18 and 30 ppma; and fewer than 25 particles that are larger than 0.3 .mu.m in size.
A cross section of a typical semiconductor structure (e.g., a complementary metal-oxide-semiconductor (CMOS) structure) is illustrated in FIG. 1. The structure has metal 12 and oxides (insulators) 14 deposited on the surface of a substrate 10 (semiconductor wafer). The p regions 17 and n regions 20 are typically formed by either implantation or diffusion into the substrate 10. These n and p device regions are confined to the surface layers and are typically less than about 1 to 2 .mu.m thick. The topography formed by the metal and oxide depositions is typically less than 1 .mu.m. Thus, a variety of implantations, diffusions, and depositions of different materials are made in and on a wafer substrate during processing.
Wafers can be rejected during device processing or during post-process device testing. Rejected wafers can have epitaxial layers, diffusions, contacts, gate conductors (such as polysilicon or polycides or metals), and insulators. Removal of these layers and depositions is required to restore a wafer to its original, defect-free condition.
When a wafer is rejected during processing, for reasons such as physical damage to layers, misprocessing, or electrical characteristics being outside a specification, the wafers are typically removed from further processing and are used for purposes other than making electrical chips. Many times, the defect is caused by equipment failure or equipment that is out of calibration. Sometimes, such as in resists or metal layers, the individual process step is reworked easily and the resulting layer becomes acceptable. A simple rework is not feasible, however, when more than one process step leads to an off-specification condition. In these cases, the wafer lot is typically discarded.
The prior art does not offer a technologically and economically feasible solution to restore wafers to their original, defect-free form. For example, it is difficult to selectively or controllably etch out the dopant regions because they are present not just as layers, but as regions within layers in association with oxide regions. The dopant regions are typically silicon with varying amounts of dopants. In CMOS wafers, a typical topography is about 1 .mu.m at the end of device processing. This topography is created primarily by oxide isolation, gate electrode stack, or both. If the gate stack and isolation oxide are entirely removed, the wafer will still have some topography from the removal of isolation oxide because it is formed by in-situ conversion of silicon or by cutting a trench and filling it with oxide. Mechanically planarizing this substrate while removing the topography is difficult unless a large amount of silicon is removed by polishing. Such a polishing process is both difficult and expensive. For example, if more than one material is present, such as a gate electrode or an oxide along with silicon, polishing is very difficult because different materials polish very differently.
In practice, most rejected wafers are simply coated with a thick layer of plasma deposited oxide to insulate the substrate and are then used as a "line monitor." This is not an efficient use of the rejected wafers. Therefore, there is a need for a process that can remove the unwanted layers of the rejected wafers with a minimum loss of the wafer thickness. Such process steps need to be compatible with the silicon manufacturing process and preferably restore the rejected wafer to the new wafer specifications defining thickness, uniformity, and electrical values.
Although the art of semiconductor fabrication is well developed, there remain some problems inherent in this technology. One particular problem is restoring a rejected or defective semiconductor wafer to its original form. Therefore, a need exists for a method which restores semiconductor wafers that have been rejected during processing to their original new wafer specifications for future use in device manufacturing.